ENEL373-25S1 (C) Semester One 2025

Digital Electronics and Devices

15 points

Details:
Start Date: Monday, 17 February 2025
End Date: Sunday, 22 June 2025
Withdrawal Dates
Last Day to withdraw from this course:
  • Without financial penalty (full fee refund): Sunday, 2 March 2025
  • Without academic penalty (including no fee refund): Sunday, 11 May 2025

Description

Digital electronics: combinational and sequential logic, finite state machines, reprogrammable logic devices, digital memory devices, field programmable gate arrays. Logic circuit description, design, testing and implementation: VHDL, register transfer level description, test-benches, practical considerations. Digital devices: MOSFETs, CMOS, fabrication technologies, application-specific integrated circuits for optoelectronics, radio frequency electronics and power electronics.

This is an in-depth course that takes logic theory and applies it to the analysis, synthesis
and simulation of digital logic circuits; and the application and theory of implementing
electronics devices. The course also covers the implementation of circuit designs using a
hardware description language with specific application to the design of simple
microprocessors and peripherals. We also cover the digital assumption made of switching
analogue circuits, look at the physical implementation of transistors, circuits based on
them and interconnecting components. Students are assumed to have knowledge in basic
computer architecture and electronics.

Topics include:
1. Digital Logic: Truth tables, Boolean expressions, sets; Boolean logic and manipulation;
SOP and POS form; sufficiency; logic minimisation and K-maps; combinational logic;
sequential design and finite state machines.
2. Computer Architecture: Hardware description language design (VHDL); register
specification; adders; arithmetic and logic units; basic execution unit design; integration
of design units to build a simple state controller.
3. CMOS Implementation of Digital Circuits: Logic thresholds; rise and fall times; noise
margins; CMOS inverter; physical implementation on digital characteristics; CMOS
fabrication; synthesis of logic in CMOS; effect of capacitance; gate-power prediction, RS
flip-flop realisation in CMOS.
Classification: In-Confidence
4. System-on-a-chip: SoC components; interconnects; external chip interfaces;
optoelectronic components; photodetectors; lasers; radio frequency devices; RF transistors
and diodes.

Learning Outcomes

  • At the conclusion of this course you should be able to:

  • LO1: Represent, manipulate, optimise and synthesise logical expressions for digital circuits using algebraic, graphical, numerical and modelling techniques, hardware description language and associated tools (WA1, WA2)

  • LO2: Design simple microprocessors, including integrating peripheral devices (WA3, WA4, WA5)

  • LO3: Describe, analyse, and evaluate the operational characteristics of CMOS (WA2, WA3, WA4, WA5)

  • LO4: Evaluate and optimise the performance of digital electronic devices and components (WA3, WA4, WA5).

  • LO5: Communicate the design of electronic devices to peers in graphical and written form (WA10)
    • University Graduate Attributes

      This course will provide students with an opportunity to develop the Graduate Attributes specified below:

      Critically competent in a core academic discipline of their award

      Students know and can critically evaluate and, where applicable, apply this knowledge to topics/issues within their majoring subject.

      Employable, innovative and enterprising

      Students will develop key skills and attributes sought by employers that can be used in a range of applications.

Prerequisites

Restrictions

ENEL391 and ENCE362

Timetable 2025

Students must attend one activity from each section.

Lecture A
Activity Day Time Location Weeks
01 Wednesday 10:00 - 11:00 Meremere 108 Lecture Theatre
17 Feb - 6 Apr
28 Apr - 1 Jun
Lecture B
Activity Day Time Location Weeks
01 Friday 15:00 - 16:00 Meremere 108 Lecture Theatre
17 Feb - 6 Apr
28 Apr - 1 Jun
Lecture C
Activity Day Time Location Weeks
01 Thursday 10:00 - 11:00 E9 Lecture Theatre
17 Feb - 6 Apr
28 Apr - 1 Jun
Lab A
Activity Day Time Location Weeks
01 Monday 09:00 - 11:00 Elec 210 Electronics Lab
17 Feb - 6 Apr
28 Apr - 1 Jun
02 Thursday 15:00 - 17:00 Elec 210 Electronics Lab
17 Feb - 6 Apr
28 Apr - 1 Jun
03 Friday 16:00 - 18:00 Elec 210 Electronics Lab
17 Feb - 6 Apr
28 Apr - 1 Jun
Tutorial A
Activity Day Time Location Weeks
01 Friday 12:00 - 13:00 Rehua 005 (28/2, 28/3, 2/5-30/5)
C2 Lecture Theatre (14/3)
24 Feb - 2 Mar
10 Mar - 16 Mar
24 Mar - 30 Mar
28 Apr - 1 Jun
Tutorial C
Activity Day Time Location Weeks
01 Friday 12:00 - 13:00 C2 Lecture Theatre
17 Feb - 23 Feb

Examinations, Quizzes and Formal Tests

Test A
Activity Day Time Location Weeks
01 Monday 19:00 - 20:00 A2 Lecture Theatre
24 Mar - 30 Mar
02 Monday 19:00 - 20:00 E9 Lecture Theatre
24 Mar - 30 Mar

Course Coordinator

Ciaran Moore

Lecturer

Steve Weddell

Assessment

Assessment Due Date Percentage 
Project Milestone 6%
Test 20%
Project Demonstration 6%
Project Report 6%
Project Code Submission 7%
CMOS Assignment 15%
Final Exam 40%

Textbooks / Resources

Recommended Reading

A.S. Sedra and K.C. Smith; Microelectronic Circuits ; 6th Edition; New York : Oxford University Press, 2011.

J.L. Hennessy and D.A. Patterson; Computer Architecture: A Quantitative Approach ; 3rd Edition;

J.R. Wakerly; Digital Design Principles and Practices ; 3rd Edition;

P. Ashenden; A Student's Guide to VHDL ; 2nd Edition;

S. Brown and Z. Vranesic; Fundamentals of Digital Logic with VHDL Design ; 4th Edition;

S.M. Sze and M.K. Lee; Semiconductor Devices - Physics and Technology ; 3rd Edition;

Additional Course Outline Information

Academic integrity

AI tool use
Generative AI Tools Are Not Restricted for the Project Milestone and Project Demonstration.
In these assessments, you are permitted to use generative artificial intelligence (AI) to assist
you in any way within the bounds of academic integrity.

Generative AI Tools Are Permitted for Certain Parts of the Project Report, Project Code Submission
and CMOS Assignment.
For the project report and CMOS assignment, you are permitted to use generative artificial
intelligence (AI) solely for the purpose of improving the clarity of your writing. No other use of
generative AI is permitted. To assist with maintaining academic integrity, you must appropriately
acknowledge any use of generative AI in your work. Please include a statement of acknowledgement
with your work, clearly indicating which AI tools were used and how they contributed to your
assessment.

For the project code submission, you are permitted to use generative artificial intelligence (AI)
for the purpose of developing and improving your VHDL code. No other use of generative AI is
permitted. To assist with maintaining academic integrity, you must appropriately acknowledge any
use of generative AI in your work. Please include a statement of acknowledgement in each relevant
file, clearly indicating which AI tools were used and how they contributed to your assessment.

Generative AI Tools Cannot Be Used for the Test and Exam.
In these assessments, you are strictly prohibited from using generative artificial intelligence
(AI) to generate any materials or content related to the assessment. This is because the
requirements of these assessment are for students to demonstrate human knowledge and skill
acquisition without the assistance of AI. The use of AI-generated content is not permitted and may
be considered a breach of academic integrity. Please ensure that all work submitted is the result
of your own human knowledge, skills, and efforts.

Scaling of marks
Scaling is used to maintain consistency across the courses and fairness for students. In the
Faculty of Engineering target course GPAs are calculated based on the performance of the cohort of
students taking the course in the previous year. Scaling of the raw total course marks is normally
performed so that when converted to grades (using UC Grade Scale) the outgoing GPA is in line with
the target GPA for a course. Scaling up or down can
occur. The Grading Scale for the University is available

Classification: In-Confidence
at  https://www.canterbury.ac.nz/study/study-support-info/study-related-topics/grading- scale.



Dishonest Practice
Plagiarism, collusion, copying and ghost writing are unacceptable and dishonest practices.
•    Plagiarism is the presentation of any material (test, data, figures or drawings, on any medium
including  computer  files)  from  any  other  source  without  clear  and adequate acknowledgment
of the source.
•    Collusion is the presentation of work performed in conjunction with another person or persons,
but submitted as if it had been completed only by the named author(s).
•    Copying is the use of material (in any medium, including computer files) produced by another
person(s) with or without their knowledge and approval.
•    Ghost writing is the use of another person(s) (with or without payment) to prepare all or part
of an item submitted for assessment.

Do not engage in dishonest practices. The Department reserves the right to refer dishonest
practices to the University Proctor and, where appropriate, to not mark the work.

Mahi ā-Ākonga | Workload (expected distribution of student hours, note 15 points = 150 hours):

Contact Hours

Lectures: 36 hours
Tutorials: 9 hours
Workshops: 0 hours
Laboratories: 20 hours

Independent study

Review of lectures: 36 hours
Test and exam preparation: 18 hours
Assignments: 8 hours
Tutorial preparation: 14 hours
Project work outside of laboratories: 9 hours

Total 150 hours

Indicative Fees

Domestic fee $1,122.00

International fee $6,238.00

* All fees are inclusive of NZ GST or any equivalent overseas tax, and do not include any programme level discount or additional course-related expenses.

For further information see Electrical and Computer Engineering .

All ENEL373 Occurrences

  • ENEL373-25S1 (C) Semester One 2025