Special Topic

Subject to the approval of the Head of Department

Timetable Note

Please note that the course activity times advertised here are currently in draft form, to be finalised at the end of January for S1 and whole year courses, and at the end of June for S2 courses.

Please hold off enquiries about these times until those finalisation dates.



Time Commitment: 150 hours
• 24hr Lecture hours (2x1hr/week – 12 weeks)
• 10hr Laboratory – formal help sessions on VHDL and Verilog programming (5x2hr/week – 5 weeks)
• 30hr Self directed learning (lecture prep)
• 70hr Project work
• 16hr Test and Examinations (including prep time)

Course Coordinator

Andrew Bainbridge-Smith

Lecturer: Andrew Bainbridge-Smith, Senior Lecturer Above the Bar
Lecturer: Professor Dali Wang, Erskine Fellow from Christopher Newport University, Virginia, USA

Assessment

Approximate Agenda:
1. General computer architecture - Introduction, gate design to simple computing units, VHDL/Verilog
2. Memory organisation - Memory hierarchy, cache design
3. Concurrency and parallelism - bit, instruction and thread parallelism; mutual-exclusion; race-conditions; idempotence; locks; Tomasulo’s algorithm and Peterson’s algorithm
4. Specialised architectural designs - Superscalar, multithreading
5. Unconventional designs - systolic-arrays, number systems and arithmetic, hardware NNs
6. GPUs - concepts and uses
7. Quantum computing* - concepts and uses – This topic is yet to be confirmed

Project:
An individual project where the student is required to undertake a scholarly review of an approved topic in computer architecture.  The student will be required to produce a written report including:
• an explanation of the topic aimed at peers in the course (Learning Outcome 1)
• a literature review on the topic, preferably including a meta-review and a number of recent publications in the area (Learning Outcome 4)
• an implementation (or salient part thereof) in VHDL/Verilog of the topic – outline of the design in the report, with actual code as a supplementary submission (Learning Outcome 2)
• to conduct some basic performance measurements of their implementation and to report on these (Learning Outcome 5)

The project work is supported by a weekly 2 hour workshop session where both VHDL and Verilog programming is introduced to students.  Students are only required to develop and implement their design ideas in one of the languages for their project, but are expected to develop understanding in both.

Mid-Semester Test & Final Exam:
These tests, aimed as assessing Learning Outcomes 1-3, will be designed to ensure students have adequate breadth of understanding and knowledge of the entire course.

Indicative Fees

* All fees are inclusive of NZ GST or any equivalent overseas tax, and do not include any programme level discount or additional course-related expenses.